Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine

Most modern security protocols and security applications are deened to be algorithm independent, that is, they allow a choice from a set of cryptographic algorithms for the same function. Therefore a key-search machine which is also deened to be algorithm independent might be interesting. We researched the feasibility of a universal key-search machine using the Data Encryption Standard (DES) as an example algorithm. Field Programmable Gate Arrays (FPGA) provide an ideal match for an algorithm independent cracker as they can switch algorithms on-they and run much faster than software. We designed, implemented and compared various architecture options of DES with strong emphasis on high-speed performance. Techniques like pipelining and loop unrolling were used and their eeectiveness for DES on FPGAs investigated. The most interesting result is that we could achieve data rates of up to 403 Mbit/s using a standard Xilinx FPGA. This result is by a factor 31 faster than software implementations while we are still maintaining exibility. A DES cracker chip based on this design could search 6.29 million keys per second.